Fan Out Chip Scale Systems in Package processed on panel type reconstructed wafers typically contain top and bottom side active and passive components encapsulated by top and bottom epoxy molding compound in either liquid or granular form. These packages are processed in full panel processes up to the final device singulation.
This panel level processing is inherently suseptable to total thickness variation and/or warpage, resluting in problematic backend processing, particularly in the steps including molding, back grinding, laser marking, laser ablation, ball placement, and singulation.
Typically, annealing and/or leveling of the reconstructed wafer in panel form is required multiple times throughout the process. The leveling/annealing is required because the multiple layering process for Fan Out Wafer Level Packaging uses different materials that have different Coefficents of Thermal Expansion (CTE) and glass transition temperatures (Tg), resulting in these material layers expanding and contracting at different rates, which causes the re-constructed wafer to warp. When the re-constructed wafer warps, it is not possible to process through the next process steps. This adds cost and cycle time. Furthermore, these annealing and/or leveling steps are not always effective in removing warpage or mold thickness variation and do not always result in a tighter tolerance capability. Thus, the process is impacted and the final packaging yield may be lower than optimal.
U.S. Pat. Nos. 9,676,619 (Zhao et al) and 7,883,992 (Furuta) teach methods of dicing a wafer into strips, but these processes have nothing to do with the process of the present disclosure.